This invention relates generally to the testing of CMOS integrated circuits, and more particularly the invention relates to the use of power supply current (I.sub.DDq) measurements for the testing of the integrated circuits.
I.sub.DDq testing is a method for testing VLSI circuits by detecting elevated levels of quiescent current caused by defects in the circuit. As applied today, I.sub.DDq is measured on a set of test vectors and each measurement from the set is compared to a threshold value. If a measurement is higher than the threshold, the test fails; if all measurements are below the threshold, the test passes.
Despite increasing popularity and ever more widespread use of I.sub.DDq testing in recent years, an open question still exists as to what level of current to use as the I.sub.DDq pass/fail threshold. Setting the limit incorrectly carries a heavy penalty. If the limit is too high, bad dies may escape testing, which defeats the purpose of I.sub.DDq testing aimed at detecting defects that are unlikely to be detected by voltage testing. If the limit is too low, good dies may be rejected, which leads to unnecessary yield loss and, hence revenue loss.
The present invention introduces the notion of a current signature as a means for addressing this problem. The potential of current signatures for allowing dies with harmful defects to be identified--even if they have only a low level of defect current--without imposing a restrictively low pass/fail threshold has been demonstrated via several examples taken from a large CMOS circuit design.